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MC74VHC1GT126 Noninverting Buffer / CMOS Logic Level Shifter
with LSTTL-Compatible Inputs
The MC74VHC1GT126 is a single gate noninverting 3-state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT126 requires the 3-state control input (OE) to be set Low to place the output into the high impedance state. The device input is compatible with TTL-type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V CMOS Logic while operating at the high-voltage power supply. The MC74VHC1GT126 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
Features http://onsemi.com MARKING DIAGRAMS
5 5 1 SC-88A/SOT-353/SC-70 DF SUFFIX CASE 419A W3 M G G M 1 5 5 1 TSOP-5/SOT-23/SC-59 DT SUFFIX CASE 483 W3 M G 1 W3 M G G
* * * * * * * * *
High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2 V CMOS-Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 62; Equivalent Gates = 16 Pb-Free Packages are Available
1 2 3 4 5 OE IN A GND 1 2 3 4 OUT Y A Input L H X 5 VCC
= Device Code = Date Code* = Pb-Free Package
(Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location.
PIN ASSIGNMENT
OE IN A GND OUT Y VCC
FUNCTION TABLE
OE Input H H L Y Output L H Z
Figure 1. Pinout (Top View)
OE IN A OUT Y
ORDERING INFORMATION Figure 2. Logic Symbol
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
February, 2007 - Rev. 13
Publication Order Number: MC74VHC1GT126/D
MC74VHC1GT126
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD qJA TL TJ Tstg VESD DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power Dissipation in Still Air Thermal Resistance Lead Temperature, 1 mm from Case for 10 s Junction Temperature Under Bias Storage Temperature ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SC-88A, TSOP-5 SC-88A, TSOP-5 VOUT < GND; VOUT > VCC Characteristics Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -20 +20 +25 +50 200 333 260 +150 -65 to +150 > 2000 > 200 N/A 500 Unit V V V mA mA mA mA mW C/W C C C V
ILatchup
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 5.0 V 0.5 V Characteristics Min 3.0 0.0 0.0 -55 0 Max 5.5 5.5 VCC +125 20 Unit V V V C ns/V
Device Junction Temperature versus Time to 0.1% Bond Failures
NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C
1 1 10 1000
Figure 3. Failure Rate vs. Time Junction Temperature
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5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns DC ELECTRICAL CHARACTERISTICS
Symbol tPLH, tPHL Symbol VIH tPLZ, tPHZ tPZL, tPZH IOPD ICCT VOH Cout VOL CPD ICC IOZ Cin VIL IIN Maximum Output Enable TIme,OE to Y (Figures 4 and 5) Maximum Three-State Output Capacitance (Output in High Impedance State) Maximum Input Capacitance Maximum Output Disable Time,OE to Y (Figures 4 and 5) Parameter Maximum Propagation Delay, A to Y (Figures 3 and 5) Maximum 3-State Leakage Current Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Parameter Minimum High-Level Input Voltage Power Dissipation Capacitance (Note 5) VIN = VIH or VIL VOUT = VCC or GND VOUT = 5.5 V Input: VIN = 3.4 V Other Input: VCC or GND VIN = VCC or GND VIN = 5.5 V or GND VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = - 4 mA IOH = - 8 mA VIN = VIH or VIL IOH = - 50 mA VCC = 5.0 0.5 V RL = RI = 500 W VCC = 3.3 0.3 V RL = RI = 500 W VCC = 5.0 0.5 V RL = RI = 500 W VCC = 3.3 0.3 V RL = RI = 500 W VCC = 5.0 0.5 V Test Conditions VCC = 3.3 0.3 V CL = 15pF CL = 50pF Test Conditions
MC74VHC1GT126
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CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF VCC (V) 0 to 5.5 5.5 0.0 5.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 5.5 3.0 4.5 5.5 2.58 3.94 Min 2.9 4.4 1.4 2.0 2.0 Min TA = 25C TA = 25C Typ 0.0 0.0 3.0 4.5 Typ 4.8 7.0 6.5 8.0 3.6 5.1 5.4 7.9 3.8 5.3 5.6 8.1 6 4 0.25 0.1 1.35 0.36 0.36 0.53 0.8 0.8 Max 9.7 13.2 Max 8.0 11.5 8.0 11.5 0.5 1.0 0.1 0.1 6.8 8.8 5.1 7.1 5.5 7.5 10 Typical @ 25C, VCC = 5.0 V 2.48 3.80 Min Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.9 4.4 1.4 2.0 2.0 TA 85C TA 85C 1.0 2.5 8.0 10.0 9.5 13.0 9.5 13.0 11.5 15.0 Max 1.50 0.44 0.44 0.53 0.8 0.8 Max 6.0 8.0 6.5 8.5 5.0 0.1 0.1 14 10 20 -55 TA 125C -55 TA 125C 2.34 3.66 Min Min 2.9 4.4 1.4 2.0 2.0 1.0 2.5 8.5 10.5 11.5 15.0 10.0 12.0 14.5 18.0 12.0 16.0 Max 1.65 0.52 0.52 0.53 0.8 0.8 Max 7.5 9.5 0.1 0.1 10 10 40 pF Unit ns Unit V mA mA mA mA mA pF pF ns ns V V V
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MC74VHC1GT126
SWITCHING WAVEFORMS
OE VCC GND tPZL Y 50% VCC tPZH Y 50% VCC tPHZ tPLZ HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE
A tPLH
50% tPHL 50% VCC
VCC GND
50%
Y
Figure 4. Switching Waveforms
Figure 5.
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST
TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6. Test Circuit
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
ORDERING INFORMATION
Device MC74VHC1GT126DF1 M74VHC1GT126DF1G MC74VHC1GT126DF2 M74VHC1GT126DF2G MC74VHC1GT126DT1 M74VHC1GT126DT1G Package SC-88A / SOT-353 / SC-70 SC-88A / SOT-353 / SC-70 (Pb-Free) SC-88A / SOT-353 / SC-70 SC-88A / SOT-353 / SC-70 (Pb-Free) TSOP-5 / SOT-23 / SC-59 TSOP-5 / SOT-23 / SC-59 (Pb-Free) 3000 / Tape & Reel Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC74VHC1GT126
PACKAGE DIMENSIONS
SC-88A, SOT-353, SC-70 CASE 419A-02 ISSUE J
A G
5
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A-01 OBSOLETE. NEW STANDARD 419A-02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
S
1 2 3
-B-
DIM A B C D G H J K N S
D 5 PL
0.2 (0.008)
M
B
M
N J C
INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087
MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20
H
K
SOLDERING FOOTPRINT*
0.50 0.0197
0.65 0.025 0.65 0.025 0.40 0.0157
mm inches
1.9 0.0748
SCALE 20:1
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT126
PACKAGE DIMENSIONS
TSOP-5 CASE 483-02 ISSUE F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00
NOTE 5 2X
D 5X 0.20 C A B
5 1 2 4 3
0.10 T 0.20 T L G A B S
M K
DETAIL Z
2X
DETAIL Z
J C 0.05 H T
SEATING PLANE
SOLDERING FOOTPRINT*
1.9 0.074
0.95 0.037
2.4 0.094 1.0 0.039 0.7 0.028
SCALE 10:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT126/D

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